14.Aug.2003
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Mai Logic: Information About Articia P Chipset
Mai Logic has made known some information about the Articia P chipset. This information may be read in the PDF document under the title link. Excerpts from the document:
Articia P's groundbreaking architecture enables five buses to run concurrently in one package. The five buses are CPU bus, memory bus, and three configurable peripheral buses-- 32-bit AGP4X for industry-strength multimedia performance, 64-bit 133/66MHz PCIX for high-bandwidth connectivity, and 32-bit 66/33MHz PCI for legacy, low-speed devices.
With its 166 MHz Front Side Bus, 333 MHz DDR memory controller, superb AGP4X core logic, dual 64-bit PCIXs, programmable Interrupt Controller, DMA controllers, integrated Clock Generator, and Global Timers, Articia P yields an unbeatable mix of power, performance, and value.
Articia P engineering samples are expected to be available in Q3, 2003.
For any inquiries, please email us at marketing@mai.com. (nba) (Translation: dm)
[News message: 14. Aug. 2003, 19:03] [Comments: 0]
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